Pixel buffer circuits for implementing improved methods of displaying grey-scale or color images

ABSTRACT

A device such as a display device or a spatial light modulator can store pixel data in a plurality of small circuit coupled to pixel mirrors and simultaneously drive these pixel mirrors a frame at a time. This device is particularly beneficial for implementing improved image quality techniques which can convert binary images to grey-scale images and/or separate red, green and blue images into color images and displaying those images using the natural process of integration which occurs when a person views images at sufficiently high rates.

RELATED APPLICATIONS

[0001] This application is a continuation-in-part of U.S. patentapplication Ser. No. 08/505,654, the contents of which are incorporatedherein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates generally to an apparatus and method forimproving image quality and in particular to an apparatus and method forconverting binary images to grey-scale or color images and forconverting a series of red, green, and blue analog images to colorimages, and then either displaying those images or driving a spatiallight modulator.

[0004] More specifically, this invention relates to binary and analogframe buffer pixel devices and to frame buffer type devices and methodsfor implementing improved methods of displaying images or of drivingspatial light modulators.

[0005] 2. Background of the Related Art

[0006] It has been known that when a person views a rapidly cycledthrough sequence of binary images, the person may, if the rate andduration of images is proper, temporally integrate such that thatsequence of binary images and the sequence in turn appears to begrey-scale images. This integration phenomenon is of particular interestwith the arrival of high speed binary displays. Such devices are used,for example, in projection display systems, head-up displays and headmounted displays. There exist small fast high resolution displays whichare essentially binary in nature such as the Digital Mirror Device(DMD), made by Texas Instruments, active matrix electro-luminescence(AMEL) field emission display (FED) as well as actively addressedferro-electric liquid crystal devices. These technologies are capable ofproducing many thousands of binary images per second, depending on thenumber of pixels per frame, etc . . .

[0007]FIG. 1A shows a series of binary images 105 which could be viewedby a person in the manner described above. Each frame F1-Fm will becomprised of a series of bits that are either 1 (ON) or 0 (OFF). Thatis, the series F1-Fm of frames as well as each individual frame isactually a series of bits which must eventually be displayed in order tomake it possible for the person viewing the binary images to perform theintegration discussed above. FIG. 1A further shows pixels Pj in general,and P1-P4, in particular, as-representative pixels. As each frame F1-Fmis displayed for a time t, some of the pixels Pj will be a logical 1 andsome will be a logical 0. In order for a person to view images producedby frames F1-Fm, a display device is required.

[0008] A problem with the above approach is that a display device whichdisplays the group of binary images 105 must be capable of responding inthe time t (which relates to the frame rate 1/t). This places alimitation on which displays can be used. Namely, only those displaydevices can be used which have response rates at least as great as 1/tHz or frames per second. However, the integration process requires thatt be small, otherwise the display would appear to flicker and not appearto provide a grey-scale.

[0009] Currently, there are a variety of display devices which might beused to output the above discussed subframes. Liquid crystal on silicon(LCOS) devices which have been designed as displays (or spatial lightmodulators) have used pixel designs which can be categorized as beingeither “dynamic” or “static”. A static pixel design has a memory elementat each pixel, which can store the pixel data indefinitely without theneed for periodic refresh cycles. This is analogous to SRAM (staticrandom access memory) in computer memory. A dynamic pixel stores datacapacitively and requires a periodic refresh to compensate for leakageof the stored charge, analogous to DRAM (dynamic random access memory).

[0010] Both of these types of displays share the property that as thearray of pixels is addressed in sequence, row-at-a-time, the liquidcrystal begins to update to the new data immediately once the row isaddressed. It happens that a reasonably high resolution displays, suchas 1024 by 1024 pixels, the electronic refresh time is comparable orlonger than the liquid crystal switching time. For example, if data issupplied to the display through 32 data wires running at 50M bits/sec,such an array of pixels takes approximately 690 microseconds to update.The liquid crystal switches in approximately 100 microseconds. It isvalid, therefore, to view the display as being updated in a sweepingmotion across its area.

[0011] In some applications, it would be advantageous to have the dataon all of the display be simultaneously valid before it can be usefullyviewed. Examples of such applications include most coherent applicationssuch as optical correlators, optical beam steerers etc . . . , anddisplay applications where precise synchronization with other parts ofthe system, such as an illuminated source, is required.

[0012] Current pixel designs using liquid crystal displays ormicrodisplays fall into two major categories, namely, single transistorpixel systems and static pixel systems. There are a number of variationsto these types of designs, but all relate generally to one of these twoapproaches.

[0013]FIG. 1B shows a schematic of a single transistor pixel circuit 701which is part of a conventional single transistor pixel array system.Such systems are used in the so-called active matrix type computerscreens as well as in some silicon backplane microdisplays which useliquid crystal displays. The entire array of pixels is formed such thatall of the pixels circuits 701 in a row of the display share a gate wire705 and all of the pixel circuits in a column share a data wire 710 (orvice versa). Each pixel circuit 701 includes a transistor 714 and apixel mirror or window electrode 718.

[0014] Displays using circuit 701 are updated a row-at-a-time. Inparticular, gate wire 705 is activated, thereby activating alltransistors 714 on a single row of pixels on the display. Uponactivation of gate wire 705, charge flows through transistor 714,thereby bringing the pixel mirror 718 to the same voltage as data wire710. Device 718 can be a pixel mirror, electrode window, or pixelelectrode and hence these will be used interchangeably throughout thisspecification. Gate wire 705 is then de-activated, thereby trapping thecharge and hence the voltage on pixel mirror 718. The voltage on pixelmirror 718 then switches the liquid crystal (not shown). There is acapacitance associated with pixel mirror 718 and the details of thedesign of such a pixel often deal with maximizing this capacitance toimprove charge storage.

[0015] Pixel circuit 701 can be used either as an analog pixel, when thevoltages on data wires 710 are driven to intermediate values, or as abinary pixel when these wires are driven to only two values—typically OVand 5 V. It must be noted, however, that this pixel display approach isnot a frame-buffer pixel as called for in the parent application to thisapplication. That is, the pixel mirrors 718 are updated a row-at-a-time.

[0016] The other type of pixel design that has been used is theso-called static pixel displays. Static pixel displays use pixels whichcontain a data-latch and possibly other circuitry. This approach hasbeen used, for example, by a research group at the University ofEdinburgh in Scotland. FIG. 1C shows a schematic of a static pixelscircuit 721 referred to as a SRAM pixel. Pixel circuit 721 includes adata latch 732 connected to array gate mere 705 and data wire 710. Pixelcircuit 721 also has a pixel mirror or electrode window 718. (Note thatgate wire 705 and data wire 710 are given the same reference numbers inFIG. 1C as they had in FIG. 1B.) Here, however, data latch 732 reads thelogic level on data wire 710 under the control of gate wire 705. A databit is stored in data latch 732 in the conventional manner that staticlatches store data and hence, the data is stored indefinitely withoutrefresh. Output 740 of data latch 732 can be directly connected to pixelmirror 718 or connected to an exclusive-or (X-OR) 750 (as shown) or anexclusive-nor (X-NOR) gate (not shown). Exclusive-or 750 (or the X-NOR)drive a pixel clock (not shown) either in-phase or out-of-phase with aglobal clock line 755 from a global clock (not shown).

[0017] X-OR 750 functions in accordance with the signal 740 output fromdata latch 732, and consequently functions in accordance with the databit stored in latch 732. For example, all pixels in the static displaydevice that have a “1” stored in latch 732 take the opposite logic valueof global clock signal 755, whereas all pixels in the static displaydevice that have a “0” stored in latch 732 take the same logic value asthe global clock signal 755. This was originally done to facilitate d.c.balancing of nematic liquid crystals used in earlier liquid crystal onsilicon devices. It has been retained by the Edinburgh group in some oftheir-fast ferroelectric devices to assist with frame-inversion, whichis another form of d.c. balancing used with FLC based devices. Hence,once these displays load a frame of data, they have the inverse of thatframe available at the pixel mirrors simply by switching the globalclock.

[0018] This pixel display approach is also not a frame-buffer pixel ascalled for in the parent application to this application. That is,although the image data are stored on the pixel array, the pixel latches732 (and hence the pixel mirrors 718) are updated a row-at-a-time, justas in the single transistor case discussed above. Note that this pixeldisplay approach is binary since latch 732 uses restoring logic to pullall nodes in the circuit to either a logic “1” or a logic “0” as doesX-OR gate 750.

SUMMARY OF THE INVENTION

[0019] Therefore, an object or the invention is to provide a displaydevice which can provide improved image quality from binary or analogdisplay devices by updating images a frame at a time.

[0020] Another object of the invention is to provide a display apparatusthat can integrate entire frames of information together beforedisplaying that information.

[0021] Another object of the invention is to provide an apparatus forachieving grey-scale images produced using binary display devices.

[0022] Another object of the invention is to provide an apparatus withone or more data storage locations at each pixel location.

[0023] Another object of the invention is that it includes pixelcircuitry, that can be arranged in a small area about the pixel.

[0024] Another object of the invention is to provide an apparatuscapable of providing an analog signal or binary signal at each pixel.

[0025] Another object of the invention is to provide an apparatus fordynamically displaying an image or an apparatus for staticallydisplaying an image.

[0026] One advantage of the invention is that it makes it possible toobserve grey-scale images using a binary display device.

[0027] Another advantage of the invention is that it significantlyreduces the time interval during which the displayed data is changing byavoiding the row by row updating of the pixels.

[0028] Another advantage of the invention is that it can be used toproduce colored grey-scale images.

[0029] Another advantage of the invention is that it can utilize liquidcrystal display devices.

[0030] Another advantage of the invention is that it can be used withstatic as well as dynamic type display systems.

[0031] One feature of one embodiment of the invention is that itutilizes inverters to drive pixel electrodes in one embodiment.

[0032] Another feature of an embodiment of the invention is that itutilizes capacitors to store information.

[0033] Another feature of the invention is that it can drive the pixelelectrodes with an analog or binary voltage.

[0034] Another feature of the invention is that it utilizes only n-FETtransistors in one embodiment.

[0035] Another feature of the invention is that in one embodiment the ONpixels in the least significant frame is displayed at approximately halftheir full duration but no change in their output or ON intensity.

[0036] Another feature is that the non-attenuated subframes are groupedtogether to reduce the rate at which the display device outputssubframes.

[0037] Another feature on an embodiment of the invention is that the ONpixels in the least significant frame is displayed at approximately halftheir full or ON intensity.

[0038] Another feature of the invention is that it can utilize pixelbuffers or a frame/image buffer.

[0039] These and other objects advantages and features are achieved bythe provision of a device comprising: a substrate having a firstsurface; a plurality of driving electrodes arranged on the first surfaceof the substrate; and a plurality of means arranged on the substrate andrespectively coupled to the plurality of driving electrodes, forreceiving image data comprised of a series of subframes and driving theplurality of driving electrodes in accordance with a switching signal.

[0040] The above and other objects, advantages and features are furtherachieved when each of the above plurality of means comprises: a firstswitch coupled to a gate signal and a data line for receiving a pixeldatum of the image data and outputting the pixel datum in accordancewith the gate signal; a first inverter coupled to the first switch forreceiving the pixel datum; a second switch coupled to a clock signal andthe first inverter; and a second inverter coupled to the switch and to arespective one of the plurality of driving electrodes, wherein the pixeldatum is transmitted from the first inverter to the second inverter inaccordance with the clock signal, and outputs the pixel datum to saidrespective one of the plurality of driving electrodes.

[0041] The above and other objects, advantages and features are furtherachieved when each of the above plurality of means comprises: a firstswitch coupled to a gate signal and a data line for receiving a pixeldatum of the data and outputting the pixel datum in accordance with thegate signal; a capacitance means coupled to the first switch forreceiving and store the pixel datum; a second switch coupled to a clocksignal and the capacitance means; and an inverter coupled to the switchand to a respective one of the plurality of driving electrodes, whereinthe pixel data is transmitted from the capacitor means to the inverterin accordance with the clock signal, and which outputs the pixel data tothe respective one of the plurality of driving electrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0042]FIG. 1A shows a series of binary images which could be viewed by aperson in the manner described above. FIG. 1B shows a schematic of asingle transistor pixel circuit 701 which is part of a conventionalsingle transistor pixel array system. FIG. 1C shows a schematic of astatic pixels circuit 721 referred to as a SRAM pixel. FIG. 1D showsschematically the same sequence of binary images shown in FIG. 1A asthey are input to a binary display device. FIG. 1E shows a series ofgroups of m frames. FIG. 1F provides a brief demonstration of theintegration process. FIG. 1G shows an example of how a series of binaryimages which will be arranged into “bit plane” binary subframes which inturn can be displayed to appear to a viewer to be an pixel image with a4 bit grey-scale.

[0043]FIG. 2A demonstrates how subframes (such as bit plane binarysubframes) can be displayed in different order within a group ofsubframes, some being advantageous over others in various situations.FIG. 2B shows how the most significant bit frames can be distributed orspread through the entire group of frames.

[0044]FIG. 3A, FIGS. 3B, and 3C show an approach for rearranging theframes such that the display system is not required to run at a rate 1/tin order to display the least significant bit (LSB) frame. FIG. 3D showsthe steps required to achieve the process shown in FIGS. 3A-3C accordingto one embodiment of the invention.

[0045]FIGS. 4A, 4B and 4C show another approach achieve a grey-scaleeffect for the case where m′=2 (corresponding to FIG. 3C) with a framerate of approximately 1/(4t). FIG. 4D shows a method for displaying agrey-scale image on a display unit with a plurality of pixels accordingto another embodiment of the invention.

[0046]FIG. 5A shows how 8 bit grey-scale images (or 3×8 bit colorimages) can be displayed using a binary display device such as thedevice of FIG. 1F. FIG. 5B demonstrates how analog image signals as wellas digital data (such as the images of FIG. 5A) can lead to binarysubframes which in turn can be displayed via the methods of FIGS. 3A-3Dand 4A-4D.

[0047]FIG. 6A shows a display which can serve as display 115 and FIG. 6Bshows a close-up view of any one of pixels Hj according to anotherembodiment of the invention.

[0048]FIG. 7A shows a first embodiment of a frame-buffer style of pixeldisplay which uses a CMOS version of a double inverter circuit(corresponding to the buffer circuit in FIG. 6B) for signal storage andregeneration. FIG. 7B shows a second embodiment of a frame-buffer styleof pixel display which uses a CMOS version of a double inverter circuitwith additional transistors for signal storage and regeneration.

[0049]FIG. 8 shows another embodiment of a frame-buffer style of pixeldisplay which uses a single inverter.

[0050]FIG. 9A shows an analog frame-buffer pixel circuit 901 accordingto another embodiment of the invention. FIG. 9B shows a schematic of ananalog frame-buffer pixel circuit 951 that uses only n-FETs and requiresone less transistor and two fewer addressing wires per pixel.

[0051]FIG. 10 shows a schematic of a two storage location version of theanalog frame buffer pixel shown in FIG. 9A according to anotherembodiment of the invention.

[0052]FIG. 11 shows one such more complex pixel circuit according to yetanother embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0053] Several embodiments of frame-buffer type devices will bediscussed. First, however, methods and apparatii for displayinggrey-scale or color images using such frame-buffer type devices will bediscussed with reference to FIGS. 1-5. Then a general buffer typedisplay device will be presented in FIGS. 6A and 6B which takesadvantage of the integration methods discussed with reference to FIGS.1-5. Specific embodiments for binary or analog buffered displays willthen be presented in FIGS. 7 through 9, some of which are dynamic(active) type displays, and some of which are static type displays.

[0054]FIG. 1D shows schematically the same sequence of binary images 105shown in FIG. 1A as they are input to a binary display device 115 whichhas hardware pixels Hj which are either on or off (bright or dark)corresponding to the respective values Pj in frames F1-Fm. Note thatalthough a 4 by 4 pixel display and images are depicted, the followingdiscussion applies to any display and frame size.

[0055] Suppose P1 is 1 (ON) for every frame F1 through Fm, P2 is 1(O-N)for frames F1 through Fm−1 and is 0 (OFF) for frame Fm, P3 is 1 ON onlyfor frames F1 and F2 and 0 (OFF) for frames F3-Fm, and P4 is 1 (ON) onlyfor frame F1 and 0 (OFF) for frames F2-Fm.

[0056] The rate at which the frames are displayed by display device 115is 1/t Hz, where t is the time between any two consecutive frames Fj andFj+1. Since P1 is ON for all frames, pixel H1 remains ON for a time mt.Since P2 is ON for frames F1 to (Fm−1), H2 is ON for a time (m−l)t.Since P3 is ON only for frames F1 and F2, H3 is ON for a time 2t. SinceP4 is ON only for frame F1, H4 is ON only for a time t. Integration isachieved as follows. If display device 115 has a quick enough responserate, a person viewing it notices that pixel H4 is slightly brighterthan those pixels which were not ON at all, i.e., all pixels Pj otherthan P1 to P4. Similarly, pixel H3 appears slightly brighter than pixelH4 since it is ON for 2t rather than t. Similarly, H1 appears brighterthan H2 because it is ON for a time mt whereas H2 is ON for a shortertime (m−1)t.

[0057] In all of the above statements, it is assumed that the time t isshort enough that a person would not actually see or notice that H4 isON for time t and then Off for the rest of the time (m−1)t, whereas H1is ON for the entire time mt. Instead, the viewer would integrate theimages together which means that to the viewer both H1 and H4 appear tobe ON, but H1 is much brighter than H4.

[0058]FIG. 1E shows a series of groups 105 of m subframes. Here, thetotal number of subframes being viewed is N, and again the rate at whicheach frame is updated is 1/t where t is the time between frames. Eachgroup 105 is integrated by the human eye of the observer viewing device115 so as to appear as a series 155 of grey-scale images 105′ eachcorresponding to the group of images 105 after integration. Here, msubframes are required to form a single grey-scale (or color) image orframe and N subframes form a sequence of grey-scale (or color) images.

[0059]FIG. 1F provides a brief demonstration of the, integrationphenomenon. In particular, FIG. 1F shows intensity output by H1-H4 ofI(P1), I(P2), I(P3) and I(P4) versus time for four points P1-P4 under ahypothetical situation. The number of subframes is m. The followingdiscussion relates to the first group 105 of subframes. Pixel H1 is ONfor the entire m subframes, H2 is ON during the third sub-frame and offfor the remaining subframes, H3 is ON for the first and second subframesand OFF for the remaining subframes, and H4 is ON for the 5th subframeand off for the remaining subframes. If the rate 1/t is sufficient suchthat integration occurs in the viewers mind, then the intensity I(Pj)would appear to be as follows (intensities are relative intensities).I(P1)=(1,1, . . . ,1)→m, I(P2)=(0,0,1,0 . . . ,l)→1, I(P3)=(1,1, . . .0,0)→2, and I(P4)=(0,0,0,0,1, . . . 0,0)→1. Note that the peak intensityis represented by the time sequence (1,1 . . . , 1) (the lowestintensity-is (0, . . . ,0)). Also, note that the intensity at point P2will appear (if properly integrated) to be the same as the intensity atpoint P4 and their order of occurrence is not noticeable. Consequently,the subframes can be interchanged within a group 105 and provide thesame grey-scale image to an observer when properly integrated by theobserver, and indeed the correct distribution of subframes may aid theprocess of integration.

[0060]FIG. 1G shows an example of how a series of 4×4 binary imageswhich will be arranged into “bit plane” binary subframes which in turncan be displayed to appear to a viewer to be a 4×4 pixel image with a 4bit grey-scale. Note that although FIG. 1G shows 4×4 pixel images, thetransverse dimensions of the images can be any two integers. Also, thesetransverse dimensions just happen to be the same as the number of bitsof grey-scale which also can be any integer. That is, a 4 bit grey-scaleis shown for discussion and demonstration purposes only.

[0061] The group 105 of subframes shown in FIG. 1G are binary subframeswhere ON pixels are represented by 1 and OFF pixels are represented by0. A total of 2⁴−1=15 such binary subframes 105 are contained in group105 for 4 bit grey-scale images. Also, since this is a 4 bit grey-scale,there need only be 4 bit plane subframes (this number can be increased,if desired). The most significant bit CMSB) subframe shows an image withall pixels that are ON or 1 for at least 8 subframes in group 105. Ascan be seen, only pixels (2,4) (which (2,4) is ON in all of thesubframes in group 105) and all of the pixels on the y=1 row, i.e.,(1,1), (2,1), (3,1) and (4,1) (which is repeated 8 times). The next mostsignificant bit (the 2²=4) or third bit rearranged into 4 sets ofbit-plane subframes. Only pixel (2,4) is ON in this example for all ofthese bit-plane subframes. The next to the least significant subframehas two pixels ON, namely, (2,4) which is ON for all subframes asdiscussed above, and (3,1) which is ON for the 8 identical subframes andfor 2 additional subframes within group 105.

[0062] The process of arranging subframes from group 105 into theso-called bit-plane subframes can be done in a wide variety of ways andis referred to here as “bit slicing”. One approach is as follows. Thebinary data which represents the stream of binary images could be storedin a computer memory in, for example, a format where an 8-bit byterepresents the grey level to be displayed by a particular pixel (in aparticular color) after integration. One way of generating subframesfrom such a representation is to simply form a 1-bit binary bit-planesubframe from each of the bits of the 8-bit byte. This would be done insoftware by performing a logical AND operation between the byterepresenting the pixel grey level and a byte containing all the “0”sexcept for a single “1” in the correct position in the byte to extractthe desired subframe. One hardware implementation could be to readdirectly the desired bit for the bit-plane subframe from the storedbyte. by constructing the memory hardware in such a way as to facilitateselectable bit-read operations instead of byte-read operations.

[0063] One difficulty or potential problem with the above approach isthat the display device 115 must be capable of responding to the time t(which relates to the frame rate 1/t). This places a limitation on whichdisplays can be used. Namely, only those display devices can be usedwhich have response rates at least as great as 1/t Hz or frames persecond.

[0064] The situation discussed with reference to FIGS. 1A, 1C-1F can beused to produce color images with grey-scale in Red, Green and Blue asfollows. Suppose that m=100, N=10,000 and t=0.1 milliseconds. Thesenumbers would make available, in one second 100 frames or: images, eachcomprised of 100 binary sub-frames (corresponding to frames 105 in FIGS.1A, 1D, and 1E) to generate one grey-scale image for one color. If acomplete color image is desired, then three grey-scale images (one eachfor red, green and blue) would be required. In that case, approximately32 subframes would be available for each Red, Green and Blue image if wewish to display 100 color images. These 32 subframes can be used toproduce 33 equally spaced grey levels which is equivalent(approximatley) to 5 bits of grey-scale for each of Red, Green and Blue.This will be discussed in more detail below.

[0065] The above phenomenon makes it possible that the subframes can bedisplayed in any order within a group 105. In addition, some orders ofdisplay of subframes may be advantageous over others as will bediscussed below. Referring to FIGS. 1D-1F, least significant bit (LSB)subframes and most significant bit (MSB) subframes are defined asfollows. A least significant bit (SB) subframe is defined to be thatsubframe in which pixels may be ON for only one time t within group 105of subframes, thus forming the least significant bit of a binaryrepresentation of a grey-scale image, and a most significant bit (MSB)subframe is defined to be that set of 2^(p−1) subframe in which some orall pixels are ON within group 105 of subframes where p is defined asthe integer for which the following holds: 2^(p−4)−2^(p−2)− . . .+2⁰=(2^(p)−1)=m, see FIG. 1F. He the LSB subframes is that singlesubframe in which the intensity may be ON to contribute the intensitycorresponding to the LSB of a grey-scale image, and the MSB subframe isthat set of 2^(p−1) for which the intensity of a pixel may be ON tocontribute the intensity corresponding to the MSE of a grey-scale image.

[0066] Namely, since all of the subframes in each group are integratedtogether, one can display each of the 5 bit planes, i.e., bit 0 (theleast significant bit or LSB), bit 1, bit 2, bit 3 and bit 4 (the mostsignificant bit or MSB) as shown in FIG. 2A. In this scheme, the leastsignificant bit (bit 0) frame is displayed for one frame or time periodt, the next bit (bit frame) for two frames or time 2t, and the mostsignificant bit (in this case for 2^(p−1)t, where p=5) for 16 frames or16t.

[0067] In practice, when the frame rates are approaching the lowerlimits for temporal integrating, it is advantageous to spread the MSBthrough the frame which corresponds to group 105 in order to removecontouring artifacts as is known in the art. FIG. 2B shows one way thismight be done. Comparing FIG. 2A with 2B, it is seen that those pixelswhich are ON for 16 subframes, i.e. for a total time 16t-therebycorresponding to the MSB or bit 4, they can be turned ON for half ofthat time or 8t, followed by pixels with bit 3 are ON for 8t, and thenre-turn ON the MSB pixels again for the remaining time 8t so that theyhave been displayed for the necessary 16t time.

[0068] It is apparent from FIGS. 2A and 2B that generation of a 24 bittime-sequential grey-scale (or color) images in this way requires a veryhigh speed display, and/or a reduction in image rate (24-bit refers to 8bit grey-scale for each of-the three colors used, which would require255 subframes for each color. Namely, display system 115 has to run fastenough to display the least significant frame, i.e., the framedisplaying the LSB.

[0069]FIG. 3A corresponds to FIG. 2A and FIGS. 3B, and 3C show a methodof rearranging the frames such that display system 115 is not requiredto run at a rate 1/t in order to display the LSB. Note that FIG. 3Ashows all pixels displaying the same intensity Io and it is only theamount of time a particular pixel is displayed that results in thegrey-scale effect. The MSB subframes are those identical subframescontaining pixels which are ON to display the most significant bit. TheLSB subframe is the subframe containing pixels which are ON to displaythe least significant bit.

[0070]FIG. 3B shows how the group 105 is combined to effect a 5 bitgrey-scale. (for each of Red, Green and Blue) without requiring thatdisplay device 115 be capable of rates of 1/t. As can be seen, the raterequirement for display device 115 is reduced from 1/t to 1/(2t). Inorder to compensate for the additional time t that the LSB frames areON, the intensity of pixels in that frame is decreased by half from Ioto Io/2. The letter m′ is used to indicate the number of bits which aregrouped together to yield the LSB time. Hence, referring to FIG. 3A,m′=0 and hence no additional bit is grouped together with the LSE andthus no decrease in the requited rate of performance of display device115 is achieved. When m′=1, however, the first bit subframes and the 0thbit subframe are grouped together as shown in FIG. 3B and hence the raterequirement of display 115 is reduced by half to approximately 1/(2t).This reduction is accompanied, however, by a new requirement thatdisplay device 115 be capable of outputting three different intensitylevels, namely Io, Io/2 and 0, rather than the two intensities Io and 0for the m′=0 case. For a binary display device this may be accomplishedby modulating the illumination light at the appropriate time, ormodulating the optical output from the display device at the appropriatetime.

[0071]FIG. 3C takes the process one step further. Here, the LSB frames,the 1^(st) bit frames (frames displaying bits in the next to least bitposition) and the 2nd bit frames are grouped together. In this case, therate requirement for display device 115 is reduced by approximately 75%from 1/t to approximately 1/(4t). In this case, since the next to leastsignificant bit (bit 1) is ON just as long as the bit 2 frames are ON,their intensity is reduced by half to Io/2. Similarly, since the LSB bitframe is ON just as long as the LSB frame, the intensity of the LSBframe is reduced by half, from Io/2 as in FIG. 3B to Io/4. Hence, inthis case the rate that display 115 must be capable of functioning, isreduced by approximately 75% from 1/t to approximately 1/(4t). For theexample shown in FIGS. 2A and 2B, this means that the 10 kHz frame rateis reduced to 2.5 KHz.

[0072] The approach discussed with respect to FIGS. 3A-3C can begeneralized as follows. FIG. 3D shows steps required to generalize theprocess shown with respect to FIGS. 3A-3C. In particular, FIG. 3D showsstep 310 for receiving a series of N frames of binary images (eachinitially to be displayed at a rate of 1/t), where N is an integer.Alternatively, if grey-scale or color images are received instead ofbinary images, then step 310 is replaced by steps 310 a and 310 b.Namely, step 310 a involves receiving a series of grey-scale (or color)images and step 310 b involves forming binary subframes representingthese grey-scale (or color) images.

[0073] After either step 310 or steps 310 a and 310 b are performed,step 320 is performed. Step 310 involves arranging the series of Nframes of binary images into n groups of m binary subframes, where m isless than or equal to N. Step 330 involves attenuating the leastsignificant unattenuated subframes within each group of m subframes aswell as previously attenuated subframes. (if any) by a factor ofapproximately 2. Step 340 involves pairing up the unattenuated frames toyield approximately half as many unattenuated subframes andapproximately doubling thereby, the duration of the attenuatedsubframes. Please note, however, that by approximately {fraction (1/2)}it is meant that the attenuation could be anywhere from a few percent to20 percent or more of half The exact amount of attenuation (or variationin A intensity) could be determined by simply implementing theattenuation process for various amounts of attenuation and askingobservers or viewers which amount of attenuation is most effective. Notethat m′ is increased by 1 once step 340 has been completed. Step 350allows one to repeat the last two steps of 330 and 340 until the desiredframe rate is achieved.

[0074] The above process can be continued and m′ increased. For the caseof 8 bits, (i.e., m from FIGS. 1A, 1D, and 1E is 255), m′ from FIGS.3A-3C can range from 0 to 7. The number of subframes for m=255 is: 255for m′=0, 128 for m′=l, 65 for m′=2, 33 for m′=3, 19 for m′=4, 12 form′=5, 9 for m′=6, 8 for m′=7. The parameter m′ is the number of bitswhich have their illumination attenuated.

[0075] The above approach does result in an effective loss of opticalthroughput. That is, there is a data-rate/throughput trade-off which isshown in Table 1. Note that referring to the left part of Table 1(m′=1,2), the optical throughput is slightly reduced for a significantreduction in the frame rate required for a given image-rate.

[0076] Also note that the relative data rate is shown for two differentsituations. The first calculation corresponds to the timing which isdrawn in FIGS. 3A-3C for clarity. In dais case, the time taken todisplay a complete grey-scale image is increased slightly with m′. Thiscan be seen if one compares FIG. 3A with FIG. 3B or 3C in which one canclearly see that the overall data rate is decreased. That is, theattenuated subframes extend further to the right in FIGS. 3B and 3C thanFIG. 3A. Consequently, in practice, a second calculation can be made toadjust the data rate by shortening the frame durations from 2t (FIG. 3B)or 4t (FIG. 3C) to slightly less than that amount to achieve the datarate to perceive the same image rate. The approximate amount ofadjustment can be calculated as follows. If B_(m) is the number ofsubframes for a given m′, and if m is the number of subframes when m′=0,then as subframes are paired in order to go from FIGS. 3A to 3B to 3C,they should be shortened by a fraction of about (mt)/[(B_(m)2^(m))t]=m/[(B_(m) 2^(m))], where mt is the duration of the subframes105 with m′=0 and (B_(m) 2^(m))t is the duration of the subframes 105when for m′ not equal to 0. TABLE 1 (grey-scale level = 256) subframes255 128 65 34 19 12 9 8 m' 0 1 2 3 4 5 6 7 Rel. 100% 99.6% 98% 94% 84%66% 44% 25% throughput Rel. data 1 0.5 0.25 0.12 0.06 0.03 0.015 0.008rate (FIG. 3) Rel. data 1 0.5 0.255 0.13 0.07 0.05 0.035 0.03 rate(constant image rate)

[0077] The above table is calculated using the steps in FIG. 3D whichcan be summarized as follows. Starting with the unattenuated subframes,remove the least significant one and attenuate it to half its value andincrease its duration by a factor of two (along with other alreadyattenuated frames). Then the remaining unattenuated frames can becombined into half as many unattenuated frames. For example, to go fromm′=2 to m′=3 the process is as follows. At m′=2, there are 63unattenuated subframes and 2 attenuated ones. Taking the leastsignificant unattenuated frame, attenuate it by a factor of two (alsoattenuate the two attenuated frames by another factor of two). We nowhave 3 attenuatad subframes and 62 unattenuated subframes which areconverted to 31 unattenuated frames of double the duration. This yields34 subframes.

[0078] The effective attenuation of the illumination can be achieved inseveral ways. One approach is to modulate the intensity of theillumination applied to the entire display device 115 at the appropriatetime. Another approach is to modulate the transmission of an elementbetween the display and the viewer. Another approach is to pulsemodulate the illumination source which illuminates the display device atthe appropriate time to illuminate the attenuated subframes for ashorter duration. Another approach is to use a display device thathas-that capability of simultaneously allowing subframe data to beloaded at the rates described above but then to be displayed for ashorter time similar to the case of pulse modulated illuminationdescribed above. The illumination sources in some such devices areeasier to adjust than others.

[0079]FIGS. 4A, 4B and 4C show these two approaches for the abovediscussed case of illumination modulation corresponding to FIG. 3C(m′=2) with a frame rate of 1/(4t). In particular, FIG. 4B showsintensity modulation as discussed above. FIG. 4C, however, shows anintensity output to achieve the same or nearly the same result. Again,the intensity profiles are for the source illuminating display device115. Here, the intensity of all of the bits remains the same and it istheir duration which is varied. For example, the duration that the pixelsource is ON for the LSB is time t0, which is less than the time 4tshown in FIGS. 4A and 4B. The next to last bit or bit 1 is ON for a timet1 greater that t0 but less than 4t (otherwise it would appear as brightas a pixel with bit 2 ON). In particular, the lengths t0 and t1 areadjusted in a manner similar to the adjustment of intensity in that t1is approximately half of the total time 4t, i.e., tl is about 2t.Similarly, t2 is approximately half of t1 and hence approximately onefourth of 4t or simply t.

[0080]FIG. 4D shows a method for displaying a grey-scale image on adisplay unit with a plurality of pixels according to another embodimentof the invention. Step 410 involves receiving a series of N frames ofbinary images each to be displayed at a rate of 1/t, where N is aninteger. Alternatively, if grey-scale or color images are receivedinstead of binary images, then step 410 is replaced by steps 410 a and410 b. Namely, step 410 a involves receiving a series of grey-scale (orcolor) images and step 410 b involves forming binary subframesrepresenting these grey-scale (or color) images. Step 420 then involvesarranging the series of N frames of binary images into n groups of mbinary subframes, where m is less than or equal to N. Step 430 involvesshortening the duration of output of the least significant subframeswithin each group of m subframes as well as any previously shortenedsubframes by a factor of approximately {fraction (1/2)}. Please note,however, that “approximately” {fraction (1/2)}, means that theshortening could be about 50% + or − 20% or possibly more—this can bedetermined by simply implementing the shortening process for variousamounts of shortening and observing which amount of shortening is mosteffective. Note that m′ is in fact increased by 1 once step 440 has beencompleted. Step 450 allows one to repeat the last two steps of 430 and440 until the desired frame rate is achieved.

[0081] Display device 115 can include any time-sequential (grey-scale)display whether liquid-crystal on silicon, digital mirror devices, etc .. . Even if the light modulation mechanism is intrinsically capable ofvery high frame rates, the data rates from the display drivingelectronics as well as the display itself should be reduced for reasonsof cost and cabling convenience.

[0082] All of the above discussion can be applied to color displayswhich briefly discussed earlier. Here, the color light source may be,for example, 3 separate light sources, namely, a red light source, agreen light source and a blue light source. These color light sourcescan be, for example, a red light emitting diode, a green diode, and ablue diode, respectively or a white light source which is sequentiallyfiltered to appear red, green or blue, or a filter between the displayand the viewer which is sequentially switched to transmit red, green orblue. Each of these light sources is treated in a manner analogous tothe above light source for grey-scale. In each of these situations, theoutput intensity is not attenuated in intensity or shortened induration. Color “grey-scale” can be achieved, however, by applyingeither the steps of FIG. 3D for attenuation or the steps of FIG. 4D forduration shortening. This can be achieved for each of the light sources.That is, each of the red, green and blue light sources can be integratedby an observer as discussed above. For example, if the red light sourceoutputs frames as in FIG. 3A with m′=0, then the rate of output can bereduced to approximately {fraction (1/2)} that rate by attenuating theintensity of the red light source at the pixels in the least significantframe to approximately {fraction (1/2)} (i.e., from Io to approximatelyIo/2), and then combining the unattenuated frames in pairs of duration2t and doubling the duration of the least significant frame from t to 2tin the same manner as discussed in FIGS. 3A-3D and in particular insteps 330 and 340. This process can be repeated (see step 350 in FIG.3D). This procedure can be done for each of the red light source, greenlight source and blue light source.

[0083] Another example involves applying the method of FIGS. 4A-4D toeach of the red, green, and blue light sources. For example, if it isdesired that the red light source output frames as in FIG. 4A (whichcorresponds to m′=2), then instead of outputting the least significantframes with pixel outputs of the red light source at Io/4, the durationof the illumination or attenuation of those pixels is reduced by 4 from4t to t. Similarly, instead of outputting the next to least significantframes with pixel outputs of the red light source at Io/2, the durationof those pixels is reduced by approximately 2 from 4t to 2t as shown inFIG. 4C. This process can be repeated as in steps 450 in FIG. 3D. Thisprocedure can be done for each of the red light source, green lightsource and blue light source. Note that it may be advantages tointersperse red, green, and blue subframes to aid the integrationprocess.

[0084] In practice, color displays are typically achieved using a RGBsource where R corresponds to a subframe of pixels which are displayingred, G corresponds to a subframe of pixels which are displaying green,and B corresponds to a subframe of pixels displaying blue. Then thelight source is used to output the following subframes. Referring toFIG. 3A, suppose the corresponding series of red subframes, greensubframes and blue subframes are arranged as follows:

[0085] RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRGGGGGGGGGGGGGGGGGGGGG GGGGGGGGGGGBB BBBBBBBBBBBBBBBBBBBBBBBBBBBB . . . , where each capital lettercorresponds to a frame in FIG. 3A and this example m=31 (recall that mis the total number of subframes).I

[0086] If each of the red, green and blue sources undergoes the processof FIG. 3B via implementation of steps 310-340 one time (so that m′=1),then the least significant frame (to be attenuated) can be representedby small letters r, g, and b for red, green, and blue, respectively.Using the above nomenclature, the output during illumination, the red,green and blue sources would be: RR RR RR RR RR RR RR RR RR RR RR RR RRRR RR rr GG GG GG GG GG GG GG GG GG GG GG GG GG GG GG gg BB BB BB BB BBBB BB BB BB BB BB BB BB BB BB bb

[0087] where a space is depicted here only to make clear that two of theunattenuated frames are combined, it being understood that the spacesare analogous to the vertical lines separating frames in FIG. 3B.Typically, the RGB source outputs frames in the sequence RGBRGBRGB . . .Hence, the above could be output as RR GG BB RR GG BB . . . rr gg bb. Aspreviously discussed, however, the order of the frames may be changed toaid the process of integration. Finally, the above series of framescould also have a shortened duration (as discussed in FIGS. 4A-4CD) ofthe least significant frame as can be shown as follows: RR RR RR RR RRRR RR RR RR RR RR RR RR RR RR R GG GG GG GG GG GG GG GG GG GG GG GG GGGG GG G BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB B

[0088] where a single letter R, G, or B means that the duration of timethat the pixel is ON is approximately half as long as the other pixelsbut the intensity of those pixels is not attenuated. Here again, theorder of the frames can be altered and still appear the same to anobserver.

[0089] For m′=2, the above can is combined as follows: RRRR RRRR RRRRRRRR RRRR RRRR RRRR rrrr ssss GGGG GGGG GGGG GGGG GGGG GGGG GGGG gggghhhh BBBB BBBB BBBB BBBB BBBB BBBB BBBB bbbb cccc

[0090] where a space is analogous to the vertical lines in FIG. 3C, ands, h and c are each half the in tensity of r, g and b, and one fourth ofthe intensities of y,G, and B, respectively.

[0091] Again, it may be useful to change order within the group of mframes, the above could be output in a variety of ways including RRRRgggg BBBB rrrr GGGG bbbb RRRR GGGG BBBB BBBB . . . RRRR hhhh BBBB ssssGGGG cccc. Again, the above series of frames could also have a shortenedduration of time as discussed above with respect to FIGS. 4A-4D asfollows: RRRR RRRR RRRR RRRR RRRR RRRR RRRR RR   R GGGG GGGG GGGG GGGGGGGG GGGG GGGG GG   G BBBB BBBB BBBB BBBB BBBB BBBB BBBB BB   B

[0092] where double letters RR, GG, and BB mean that the duration of theframes is approximately half as long as for the frames RRRR, GGGG andBBBB, respectively (but the intensity is the same). Similarly, thesingle letters R, G, and B, have durations of time that is half as longas the frames RR, GG, and BB, and one fourth as long as frames RRRR,GGGG, and BBBB. Here again, the order of the frames can be altered andstill appear the same to an observer. Again, it should be understoodthat all of the attenuations and shortenings are approximate asdiscussed above.

[0093]FIG. 5A shows how 8 bit grey-scale images (or 3×8 bit colorimages) can be displayed using a binary display device such as device115 of FIG. 1F. Although 8 bit subframes are shown, it should beunderstood that any number grey-scale can be used if the applicationdemands greater or lesser precision. One way this can be done is togenerate the sequence of subframes from bit-frames derived from analogsignals. To do this the analog signal (or signals if R, G, and B havebeen separated), which represents the brightness of the image on aseries of scan lines could be sampled with an analog-to-digitalconverter (ADC). The outputs from the ADC then become the binary valuesfor the bit-frames corresponding to the value of the respective ADCoutputs. As the analog signal is repeatedly sampled, the pixels in thebit-frames are assigned values in a sequence which matches the rasterscanning pattern used in the analog signal representation.

[0094]FIG. 5B demonstrates how analog image signals as well as digitaldata (such as the images of FIG. 5A) can lead to binary subframes whichin turn can be displayed via the methods of FIGS. 3A-3D and 4A-4D. Inthe example shown in FIG. 5B, 8 bit grey-scale or 3×8 bits pixel colorare discussed, it being understood that any number of bits could beused. FIG. 5B involves either: 1) receiving images in analog form atstep 553 and converting these images into digital image data; or 2)receiving the digital images directly. Once received, these digitalimages are rearranged into bit plane subframes at step 567. Again, asdiscussed above with respect to FIG. 5A, if the digital images aregrey-scale images or color grey-scale images then step 567 involves bitslicing as shown in FIG. 5A. Alternatively, if the digital images arebinary subframes, then step 567 involves bit slicing as shown in FIG.1G. Finally, step 577 involves reordering (if desired) the resulting bitplane subframes and displaying those bit plane subframes the propernumber of times in accordance with that bit plane's grey-scale bitlocation. That is, as discussed above, if an 8 bit grey-scale isdesired, then the MSB subframe is displayed 2⁷=128 times, the next tothe MSB subframe is displayed 2⁶=64 times etc . . . , to the LSBsubframe which is displayed one time. Recall that there may beadvantages in not displaying each bit frame (especially for the MSB) alltogether or in succession. That is, sometimes, in order to avoidflicker, the MSB and other images can be split up and intermittentlydisplayed.

[0095]FIG. 6A shows a display 505 which can serve as display 115 andFIG. 6B shows a close-up view of any one of pixels Hj. Liquid crystal onsilicon (LCOS) displays or spatial light modulators could serve asdisplay 115. In particular, referring to FIG. 6A, an LCOS display 505includes a thin layer of liquid crystal 509 on a silicon substrate 511which is covered by a glass window 515. Substrate 511 includes anintegrated circuit 520 with pixels Hj.. Integrated circuit .520 is usedto apply an electric field across the liquid crystal layer 509 in orderto reorient the liquid crystal and thereby modulate a light beam that isreflected from substrate 511 as shown in FIG. 5 or in special processes,transmitted through substrate 511.

[0096] At this point, it should be noted that it is advantageous toupdate all pixels simultaneously for in situations such as in driveschemes which utilize an electrical modulation of the cover glasstransparent electrode voltage which can facilitate dc balancing. Changesin the electrical data presented to the pixel electrodes can besynchronized with changes to the color glass voltage, thereby maximizingthe efficiency of the drive scheme. It is advantageous if integratedcircuit 520 uses an area which is comparable with, or less than thatused by existing static pixel designs. Standard 1.2 micrometer CMOSdesign can be used as it has for existing static pixel designs to yieldan approximately 20 micrometer by 20 micrometer pixel area.

[0097]FIG. 6B shows a close-up view of a group of three pixels Hj suchas the three pixels 521 as well as some of the associated electronicsaccording to one embodiment of the invention. Note that FIG. 6B is onlya schematic representation of several pixels together with theirassociated electronics. In particular, a series of pixel buffers 525 arerespectively coupled to liquid crystal driving electrodes 529 of pixelsHj to integrated electronics 520. The entire group of pixel buffers 525comprise an image buffer 535. A data input 538 receives image data to beeventually displayed.

[0098] Display 505 operates as follows. New image data would be receivedvia input 538 by integrated circuit 520 and stored in frame buffer 535but not yet applied to liquid crystal layer 509. This allows theprevious image to be viewed without it being gradually displaced by thenew data. Once frame buffer 535 has been completely filled with the newdata, that new data is simultaneously transferred from pixel storageelements 522 to liquid crystal driving electrodes 529.

[0099] Note that the above scenario makes it possible to significantlyreduce the time interval during which the displayed data is changing.For example, consider using a standard LCOS device which has 1024 by1024 pixels, which addresses and begins to update the pixels arow-at-a-time. For such a standard system which includes 32 data wiresrunning at 50 Mbits/second, the displayed data is updated in about 655microseconds. However, display system 505 which replaces the old imagedata with the new image data, is limited to the switching time of thepixels and in particular, of the liquid crystal device, which is about100 microseconds. Note that pixels Hj are not necessarily static andindeed at this point a dynamic type pixel approach might be preferable.

[0100] The discussion that follows deals with examples of the systemshown in FIGS. 6A and 6B (but the circuits are not limited to such adisplay), and elements shown in those figures will have the referencenumeral from FIGS. 6A and 6B in parenthesis. The discussion appliesequally to display devices and/or spatial light modulators. That is, allpixel mirrors or pixel electrodes should be considered as elements fordriving display devices such as liquid crystal displays,electro-luminescent displays, deformable mirror displays, or as drivingelements of spatial light modulators, or for any other pixel typedisplay.

[0101]FIG. 7A shows a first embodiment of a frame-buffer style of pixeldisplay which uses a CMOS version of a double inverter circuit 761(corresponding to buffer circuit 525 in FIG. 6B) for signal storage andregeneration. This version is binary, because it uses inverters that canonly reasonably be expected to drive to 0 V or Vdd (often 5V). It isalso a dynamic pixel system, because it requires a periodic refresh tomaintain data which is capacitively stored. Note that FIG. 7A includesdashed lines which represent an alternative version of double invertercircuit 761, which will be discussed with reference to FIG. 7B. Thedashed lines are not considered part of circuit 761 in FIG. 7A, but areincluded for reference purposes.

[0102] Referring first to FIG. 7A, double inverter circuit 761 operatesas follows. A global clock (not shown) provides a global clock signal online 765 to a transistor 766. When the global clock signal on line 765is inactive, it isolates input 767 of inverter 769 from output 771 ofinverter 776. A frame of new data on data wires 778 (note that data wire778 corresponds to line 538 in FIG. 6B and also note that there is onlyone wire 778 per pixel circuit 761 which is why only one is shown inFIG. 7A and hence only a pixel datum would be present on each such wire778) is loaded into inverters 776 via transistor 781 and input 782 ofinverter 776 of the pixel displaying a row-at-a-time scheme similar tothat discussed in FIGS. 1B and IC. A single gate wire 779 is activatedwhich sets a row of inverters 776 to the new data value. When gate wires779 are deactivated, the data is stored on the input capacitance ofinput 782 of inverter 776.

[0103] Rows of pixels are sequentially addressed in the above manneruntil all the pixels of the display have new data on their inverters776. The global clock is then activated, causing transistor 766 to allowthe transfer of data from output 771 of inverter 776 to input 767 ofinverter 769. This, in turn, transfers the data to output 783 ofinverter 769 which is connected to pixel electrode 718 (whichcorresponds to electrodes 529 in FIG. 6B). Then, the global clock signalon line 765 is deactivated and the pixel datum is safely stored on input767 of inverter 769. A next frame of data is loaded onto inverters 776via data wires 778 and. transistors 781.

[0104] Pixel mirror/electrode mirror 718 supplies liquid crystal (notshown) of the display with charge throughout the switching process ofthe liquid crystal at each pixel. This is advantageous because it leadsto faster switching and more complete switching. This is especially inhigh spontaneous polarization, materials.

[0105] It should be noted that circuit 761 uses single transistors 766and 781 to drive inverters 769 and 776, respectively, and hence theremay be a possible threshold drop. Consequently, an alternativeembodiment will be presented which uses two more addressing wires andtwo more transistors to allow the full voltage swing through the passgates to the inverter inputs. This alternative embodiment is shown inFIG. 7B.

[0106]FIG. 7B shows a second embodiment of a frame-buffer style of pixeldisplay which uses a CMOS version of a double inverter circuit 791 withadditional transistors for signal storage and regeneration. This versionis also binary, because it uses inverters that can only reasonably beexpected to drive to 0 V or Vdd (often 5V). It too is a dynamic pixelsystem, because it requires a periodic refresh to maintain data which iscapacitively stored.

[0107] Referring to FIG. 7B, double inverter circuit 791 operates in amanner similar to FIG. 7A. Namely, a global, clock (not shown) providesa global clock signal on line 765 to transistor 766. A second invertedtransistor 766′, however, receives a logically reversed global clocksignal on line 765′ (i.e., the logical inverse of the clock signal online 765). When the global clock signal on lines 765 and 765′ areinactive, they isolate input 767 of inverter 769 from output 771 ofinverter 776. A frame of new data on data wire 778 is loaded intoinverters 776 via transistors 781 and 781′ in accordance with gate wires779 and 779′, respectively. Input 782 of inverter 776 of the pixelcircuit display a row-at-a-time scheme. Gate wires 779 and 779′ areactivated which sets a row of inverters 776 to the new data value. Whengate wires 779 and 779′ are deactivated, the data is stored on the inputcapacitance of input 782 of inverter 776.

[0108] Pixels are sequentially addressed by rows in the above manneruntil all the pixels of the display have new data on their inverters776. The global clock is then activated, causing transistors 766 and766′ to allow the transfer of data from output 771 of inverter 776 toinput 767 of inverter 769. This in turn, transfers the data to output783 of inverter 769 which is connected to pixel electrode 718. Then, theglobal clock signal on line 765 and the inverse clock signal on line765′ is deactivated and the pixel datum is safely stored on input 767 ofinverter 769. A next frame of data is loaded onto inverters 776 via datawires 778 and transistors 781 and 781′.

[0109] The above embodiment shown in FIG. 7B has the advantage ofavoiding possible threshold drop, but requires more area per pixel thanthat of FIG. 7A. The next embodiment shown in FIG. 8 is even morecompact than the embodiment of FIG. 7A.

[0110]FIG. 8 shows a single inverter pixel circuit 801. Pixelmirror/electrode 718, inverter 769, gate wire 779, and other elementsare given the same reference numbers as those provided in FIGS. 7A and7B where possible. Note that inverter 776 in those figures has beenreplaced by a capacitor 805 which stores data while the array is beingaddressed. This is the same approach as that described above withrespect to FIG. 7A and 7B. However, circuit 801 does not have a bufferto drive input 767 of inverter 769. Consequently, capacitor 805 shouldbe as large as possible. The only disadvantages in making capacitor 805as large as possible is the area on the chip it uses. Capacitor 805 doesnot slow down the operation of circuit 801, because, typically thecapacitance of data wire 778 is so large relatively speaking as torender the capacitance of capacitor 805 (the pixel capacitance)insignificant from the point of view of drive load. The capacitance ofcapacitor 805 depend on a variety of parameters of circuit 801 such asthe desired frequency of frame-write (or refresh) operations, the rateof charge leakage from pixel capacitor 805 (e.g., possible opticallyinduced leakage), the threshold voltages of the transistors in circuit801, and the amount of area for each pixel that can be devoted tocapacitor 805.

[0111] Referring to FIG. 8, circuit 801 operates in a manner analogousto the double inverter circuits 761 and 791 as will be explained. Asabove, global clock (not shown) provides a global clock signal on line765 to a transistor 766. When the global clock signal on line 765 isinactive, it isolates input 767 of inverter 769 from output 783 ofinverter 769. A frame of new data on data wires 778 is stored oncapacitors 805 via transistors 781 of the pixel in a row-at-a-timescheme similar to that discussed above. Single gate wire 779 isactivated which charges a row of capacitors 805 to the new data value.

[0112] Rows of pixels are sequentially addressed in the above manneruntil all the pixels of the display have new data stored on theircapacitors 805. The global clock is then activated, causing transistors766 to allow the transfer of voltage and hence an entire frame of datais transferred from capacitor 805 to input 767 of inverter 769. This inturn, transfers the data to output 783 of inverter 769 which isconnected to pixel electrode 718 a frame at a time. Then, the globalclock signal on line 765 is deactivated and the pixel data is safelystored on input 767 of inverters 769 while the next frame of datacharges capacitors 805 via data wires 778 and transistors 781. The datawhich appears at pixel mirror 718 is of the opposite polarity from thedata on data wires 778.

[0113] The above discussed circuits were pixel circuits designs whichdrive the pixel electrodes 718 to binary values. The discussion thatfollows deals with circuits that drive pixel electrodes 718 to analogvoltages.

[0114]FIG. 9A shows an analog frame-buffer pixel circuit 901 accordingto another embodiment of the invention. Note that the process ofintegrating subframes is not required for an analog pixel circuit sinceby definition an analog circuit can output grey-scale type images.However, as previously discussed, if an observer sees three separategrey scale images of red, green and blue in series (rather thansimultaneously), he or she will integrate those images together(provided they appear, at high enough rates such that the integrationoccurs. This occurs typically at frame rates beginning at approximately180 Hz (3 times 60 Hz) in a pattern of RGBRGE . . . which representschanging a liquid crystal color filter from red (R) to green (G) to blue(blue) or rotating a color wheel or sequential activation of Red, Green,and Blue light sources such as light emitting diodes. In any case, thepixel circuits represented in FIGS. 9A and 9B provide the capability ofswitching frames of analog data an entire frame at a time by capturingan entire frame at a time before displaying that frame. This makes itpossible to precisely synchronize switching from an R frame to a G frameto a B frame rather than trying to synchronize the row-by-row updatingof the prior art displays or spatial light modulators.

[0115] Furthermore, these pixel circuits will facilitate the rapiddisplay of multiple Red, Green, and Blue within the duration of a singleimage, which can provide a variety of additional benefits. For instance,in the example above, one Red, one Green, and one Blue subframe are usedto form a single color image which, in this example, lasts for onesixtieth of a second. It is advantageous to intersperse more subframesinto the time allotted for the single color image. For example, sixanalog subframes could be used (instead of three) within the {fraction(1/60)} second time period and they could be presented in the orderRGBRGB, or nine analog subframes RGBRGBRGB, or twelve analog subframesRGBRGBRGBRGB, ETC . . . This process can be extended by repeatedlydisplaying groups of RGB's within the duration of time that a singlecolor image would be displayed to achieve visually smooth motion (i.e.,{fraction (1/60)} second). In this approach, all of the Red subframescould be identical, all of the Green subframes could be identical, andall of the Blue subframes could be identical. The above discussionapplies to any order of displaying Red, Green, and Blue subframes andthey need not be displayed as Red followed by Green followed by Blue.

[0116] In this approach, the rates that these subframes are displayed isabove that of ordinary display rates. The advantages of interspersingmore subframes through the time allotted for a single color image are areduction in image flicker and a reduction in color breakup effects inmoving images. The term “color breakup” refers to a phenomenon in whichthe human visual system perceives color fringes around the edges ofmoving objects. It has also been observed that interspersing the Red,Green and Blue is much more effective in reducing image flicker andcolor breakup as opposed to displaying groups of Red subframes followedby groups of Green subframe and Groups of Blue subframes. Again, thepixel circuits discussed above and below provide hardware capable ofachieving such high display rates.

[0117] Pixel mirror 718 is driven to the data voltage level throughpull-up and pull-down transistors which are clocked as will now beexplained. Circuit 901 will be described with the premise that aprevious image is already capacitively stored on pixel mirrors 718.Again, rows of the display are sequentially addressed by activating gatelines 779 and 779′ (i.e., line 779 goes high and line 779′ goes low).Data wires 778 then charge the capacitive input 905 which is the gate ofvoltage limiting MOSFET 909 to the analog voltage on those data wires778.′ This is done for each row of the display.

[0118] Pixel mirrors 718 are simultaneously reset (set to zero volts) bya HIGH on global pull-down line 915 by pull-down transistor 917. Thisglobal pull-down line 915 can be maintained on HIGH for enough time toswitch certain liquid crystal materials if, for example, they have ahigh spontaneous polarization. Examples of such a liquid crystalmaterial is BDH. 764E which requires approximately 30 microseconds tofully switch. As it switches, the reorientation of the molecularelectric dipoles partially neutralizes the charge on the pixelelectrode. It is advantageous if the pixel electrode charge can bereplenished through the time the liquid crystal is switching, so thatthe charge neutralization does not cause a perturbation of the voltageon the electrode, and a corresponding perturbation of the desired “off”state. Another example of a liquid crystal with a permanent dipole isthe chiral smectic distorted helix ferroelectric materials made byHoffman LaRoche. Its characteristic switching time is approximately 200microseconds. All of the pixel mirrors 718 are then simultaneously setto their new analog voltages by the activation of pull-up transistors927, i.e., by setting global pull-up line 925 LOW.

[0119] The above happens as follows. Current flows from Vdd line 931through pull-up transistor 927 which is switched fully “on” and throughvoltage limiting transistor 909 to pixel mirror 718. It must be notedhere that MOSFETS undergo a phenomenon called “pinch-off” which limitsthe voltage signal which can be passed by an “on” transistor. Hence, thevoltage that can be passed is limited to the voltage on gate 905(V_(gate)) minus the threshold voltage (V_(th)) of transistors 909.Pixel mirror 718 therefore charges up to V_(gate)−V_(th), therebyallowing the previously set gate voltage to control the voltage pixelmirror 718 charges up to.

[0120] In a standard CMOS process, the n-transistor threshold is apositive quantity and so pixel mirror 718 cannot be charged upcompletely to the supply voltage Vdd.

[0121]FIG. 9B shows a schematic of an analog frame-buffer pixel circuit951 that uses only n-FETs and requires one less transistor and two feweraddressing wires per pixel. Hence, this design is more compact than thatshown in FIG. 9A. Using only n-channel transistors removes the need foran n-well at each pixel as well as a power supply rail to clamp the wellvoltage. However, this design does have another threshold voltage drop.Again, identical reference numbers are used for those elements ofcircuit 901 (FIG. 9A) which are common to circuit 951.

[0122] Referring to FIG. 9B, pass gate 781 and 781′ is replaced with asingle gate 781. Also, p-type pull-up transistor 927 has been replacedby an n-type transistor 967. Here, data voltage is transmitted directlyto voltage limiting MOSFET 909 through only n-type transistor 781.Hence, the maximum voltage that can be transmitted to gate 905 isV_(gate)−V_(th) where V_(gate) and V_(th) are the same as defined above.This in turn means that the maximum voltage which can be transmittedthrough voltage limiting transistor 909 is Vdd−2V_(th). It is possibleto arrange for the transistors in circuit 951 to have a low (perhaps afew tenths of a volt) threshold voltage V_(th) by including an extramask so that selected transistors are processed to have a different(here lower) threshold.

[0123] Other more complex implementations of pixel circuits can be madein view of the above discussion. One such complex implementationinvolves extending any of the previously described circuits to have morethan one storage location at each pixel. This can be done by having morethan one data wire going to each pixel, and simultaneously clocking dataonto more than one storage location under the control of a single gatewire. Alternatively, each pixel can have a single data wire and morethan one gate wire to control which storage location the data present onthe data wire is clocked onto. The formatting of the input data woulddetermine which approach is preferable.

[0124] A multiple storage location pixel also requires a mechanism fordetermining which storage location is used to control the pixelelectrode at a given time. This might require extra transistors andcontrol wires at each pixel, thereby increasing its complexity andphysical size. This type of complex pixel may be advantageous forswitching rapidly between images such as Red, Green and Blue images asdescribed above or for performing data reformatting such as parallel toserial conversion if data arrives on several wires to the pixel, but isread out in serial.

[0125] A schematic of a two storage location version of the analog framebuffer pixel shown in FIG. 9A is shown in FIG. 10. This schematic is amultiple storage location frame buffer pixel with two storage locationsand is based on the pixel circuit in FIG. 9A.

[0126] The circuit in FIG. 10 operates the same as described for FIG. 9Aexcept that data is simultaneously presented on both data wires 778 and778′, and simultaneously clocked onto the gates of transistors 909 and909′. Either pull-up transistor 927 pull-up transistor 927′ is activatedduring the driving sequence, thereby selecting which storage locationcontrols the pixel voltage.

[0127]FIG. 11 shows one such more complex pixel circuit 1001 accordingto yet another embodiment of the invention. Here, several bits ofdigital data can be stored at each pixel and converted locally to ananalog signal for driving mirror/electrode 718. Circuit 1001 includes adata latch 1005 which is a n-bit data latch coupled to one or more datawires 778 under the control of gate wire 779. Once the data is loadedonto data latch 1005, switch 1009 is activated with global clock signal765 and the data bits are simultaneously transferred to thedigital-to-analog converter PAC) 1014 which drives pixel mirrorelectrode 718 to the desired voltage. This approach could easily beextended to incorporate automatic dc balancing circuitry such as the XORcircuit discussed with respect to the SRAM pixel.

[0128] The approach of FIG. 11 requires a larger number of transistorsfor circuit 1001 than the circuits discussed above. For that reason, itwould be unlikely that circuit 1001 would be preferable for mostdisplays, because often it is desirable to put as many pixels aspossible in given area of silicon. However, circuit 1001 and othercomplex circuits may be advantageous for specialized applications suchas optical wavefront correction where it is typically not as importantto have a large number of pixels, but instead it is more important toaccurately control their optical state.

What is claimed is:
 1. A device, comprising: a substrate having a firstsurface; a plurality of driving electrodes arranged on said firstsurface of the substrate; and a plurality of means arranged on saidsubstrate and respectively coupled to said plurality of drivingelectrodes, for receiving and storing image data and for driving saidplurality of driving electrodes a frame at a time synchronous with aswitching-signal.
 2. The device as claimed in claim 1, wherein each ofsaid plurality of means comprises: a first switch coupled to a gatesignal and a data line for receiving a pixel datum of said image dataand outputting said pixel datum in accordance with said gate signal; afirst inverter coupled to said first switch for receiving said pixeldatum; a second switch coupled to a clock signal and said firstinverter; and a second inverter coupled to said switch and to arespective one of said plurality of driving electrodes, wherein saidpixel datum is transmitted from said first inverter to said secondinverter synchronous with said clock signal, and outputs said pixeldatum to said respective one of the plurality of driving electrodes. 3.The device as claimed in claim 1, further comprising a liquid crystallayer arranged on said first surface.
 4. The display device as claimedin claim 3, further comprising a window arranged on said liquid crystallayer, wherein said plurality of means comprises a plurality of storageelements capable of approximately simultaneously outputting said imagedata to said driving electrodes which drive said liquid crystal layer toyield an image.
 5. The display device as claimed in claim 2, whereinsaid first switch comprises a first transistor and said second switchcomprises a second transistor.
 6. The display device as claimed in chain5, wherein said first and second transistors are FETs.
 7. The displaydevice as claimed in claim 2, wherein said first switch comprises afirst pair of FETs and said second switch comprises a second pair ofFET5.
 8. The device as claimed in claim 2, further comprising a liquidcrystal layer arranged on said first surface.
 9. The device as claimedin claim 1, wherein each of said plurality of means comprises a firstswitch coupled to a gate signal and a data line for receiving a pixel ofdatum of said data and outputting said pixel datum in accordance withsaid gate signal.
 10. The device as claimed in claim 9, wherein each ofsaid plurality of means further comprises a first inverter coupled tosaid first switch for receiving said pixel datum.
 11. The device asclaimed in claim 10, wherein each of said plurality of means furthercomprises a second switch coupled to a clock signal and said firstinverter.
 12. The device as claimed in claim 11, wherein each saidplurality of means further comprises a second inverter which receivesand outputs said pixel datum to a respective one of the plurality ofdriving electrodes.
 13. The device as claimed in claim 1, wherein eachof said plurality of means comprises: a first switch coupled to a gatesignal and a data line for receiving a pixel datum of said data andoutputting said pixel datum in accordance with said gate signal; acapacitance means coupled to said first switch for receiving and storingsaid pixel datum; a second switch coupled to a clock signal and saidcapacitance means; and an inverter coupled to said switch and to arespective one of said plurality of driving electrodes, wherein saidpixel data is transmitted from said capacitor means to said invertersynchronous with said clock signal, and which outputs said pixel data tosaid respective one of the plurality of driving electrodes.
 14. Thedevice as claimed in claim 13, wherein said capacitance means comprisesa capacitor.
 15. The device as claimed in claim 13, further comprising aliquid crystal layer arranged on said first surface.
 16. The device asclaimed in claim 1, further comprising a first switch coupled to a gatesignal and a data line for receiving a pixel datum of said data andoutputting said pixel datum in accordance with said gate signal.
 17. Thedevice as claimed in claim 16, further comprising capacitance meanscoupled to said first switch for receiving and storing said pixel datum.18. The device as claimed in claim 17, further comprising a secondsearch coupled to a clock signal and said capacitance means.
 19. Thedevice as claimed in claim 18, further comprising a second switchcoupled to a clock signal and said capacitance means.
 20. The device asclaimed in claim 19, further comprising an inverter which receives andoutputs a pixel datum to said respective one of the plurality of drivingelectrodes.
 21. The device as claimed in claim 1, wherein said pluralityof means receives image data comprising a series of subframes.
 22. Thedevice as claimed in claim 21, wherein said plurality of means receivesimage data comprising a series of color subframes to be displayed inseries at sufficiently high frame rates to produce color integration ofimages to an observer.
 23. The device as-claimed in claim 21, whereinsaid plurality of means receives image data comprising a series ofbinary subframes to be displayed in series at sufficiently high framerates to produce grey-scale integration of images to an observer. 24.The device as claimed in claim 1, wherein said substrate comprises aspatial light modulator which is driven by said plurality of drivingelectrodes.
 25. The device as claimed in claim 1, further comprising aliquid crystal layer arranged on said first surface which is driven bysaid plurality of driving electrodes.
 26. A device, comprising: asubstrate having a first surface; a plurality of driving electrodesarranged on said first surface of the substrate; and a plurality ofcircuits arranged on said substrate and respectively coupled to saidplurality of driving electrodes, for receiving and storing image dataand driving said plurality of driving electrodes a frame at a timesynchronous with a switching signal.
 27. The device as claimed in claim26, wherein each of said plurality of circuits comprises: a first switchcoupled to a gate signal and a data line for receiving a pixel datum ofsaid image data and outputting said pixel datum in accordance with saidgate signal; a first inverter coupled to said first switch for receivingsaid pixel datum; a second switch coupled to a clock signal and saidfirst inverter; and a second inverter coupled to said switch and to arespective one of said plurality of driving electrodes, wherein saidpixel datum is transmitted from said first inverter to said secondinverter synchronous with said clock signal, and outputs said pixeldatum to said respective one of the plurality of driving electrodes. 28.A method for displaying a color image on a display unit with a pluralityof pixels, comprising the steps of: receiving a Red frame, a Greenframe, and a Blue frame comprising the color image to be displayedwithin a first time period corresponding to a first frame display rate;and repeatedly and interspersedly displaying said Red frame, said Greenframe and said Blue frame within the first time period at a higher ratethan said first frame display rate.
 29. The method for displaying acolor image as claimed in claim 28, wherein said repeatedly andinterspersedly displaying step comprises interspersedly displaying saidRed frame, said Green frame and said Blue frame two times each, withinsaid first time period.
 30. The method for displaying a color image asclaimed in claim 28, wherein said repeatedly and interspersedlydisplaying step comprises interspersedly displaying said Red frame, saidGreen frame and said Blue frame three times each, within said first timeperiod.
 31. The method for displaying a color image as claimed in claim28, wherein said repeatedly and interspersedly displaying step comprisesinterspersedly displaying said Red frame, said Green frame and said Blueframe N times each, within said first time period, where N is an integerwhich is greater than or equal to two.
 32. The method for displaying acolor image as claimed in claim 28, wherein said receiving stepcomprises receiving the Red frame, Green frame, and Blue framecomprising the color image to be displayed within a first time periodwhich is less than or equal to about {fraction (1/30)} of a second. 33.The method for displaying a color image as claimed in claim 28, furthercomprising repeating said receiving step followed by said repeatedlydisplaying step for a subsequent color image.
 34. The method fordisplaying a color image as claimed in claim 28, further comprisingrepeating said receiving step followed by said repeatedly displayingstep for each color image within a series of subsequent color images.35. The method for displaying a color image as claimed in claim 28,wherein said repeatedly and interspersedly displaying step comprisesrepeatedly and interspersedly displaying said Red frame, said Greenframe, and said Blue frame in any order.
 36. The device as claimed inclaim 21, wherein said plurality of means receives image data comprisinga series of analog color subframes.
 37. The device as claimed in claim22, wherein said plurality of means receives image data comprising aseries of binary color subframes.
 38. The device as claimed in claim 9,wherein said pixel datum comprises an analog quantity.
 39. The device asclaimed in claim 10, wherein said first inverter comprises a voltagelimiting transistor and said pixel datum comprises an analog quantity.40. A device, comprising: a substrate having a first surface; aplurality of driving electrodes arranged on said first surface of thesubstrate; and a plurality of circuits arranged on said substrate andrespectively coupled to said plurality of driving electrodes forreceiving and storing data, wherein each of said plurality of circuitscomprises at least two storage means for receiving and storing data fora respective one of said plurality of driving electrodes, said pluralityof circuits driving said plurality of driving electrodes synchronouswith a switching signal.
 41. The device as claimed in claim 40, whereineach of said plurality of circuits comprises at least three storagemeans for receiving and storing data for a respective one of saidplurality of driving electrodes.
 42. The device as claimed in claim 40,wherein said data comprise analog image data.
 43. The device as claimedin claim 40, wherein said data comprise binary image data.
 44. Thedevice as claimed in claim 42, wherein said analog image data comprisesanalog color image data.
 45. The device as claimed in claim 42, whereinsaid binary image data comprises analog color image data.
 46. The deviceas claimed in claim 41, wherein said image data comprises color imagedata and each of said three storage means stores a respective Red datum,Green datum and Blue datum.